蚵仔麵線好吃 wrote:
根據EE Times...(恕刪)
01新的版面看了很不習慣
所以就有點懶得更新
最近最熱的就是台積電的5nm製程了~
台積電的研發團隊是兩隊輪流上陣的
不然哪有可能馬上兩年就一代
每個team是搞個四年以上,而不是兩年...
5nm這個node還找空降來一起研發
台積電近5 個高階製程世代，都是由資深研發處長吳顯揚和曹敏輪流領軍(現在他們都升研發副總了)，分別負責隔代先進製程技術研發，其中，吳顯揚負責台積電16、7 奈米製程開發，曹敏則負責20、10 奈米製程世代，然台積電在5 奈米製程技術研發，由前高通資深製程技術處長Geoffrey Yeap 負責5 奈米技術開發。
Yeap將在今年的12月的IEDM(全世界最有名的元件國際研討會)發表TSMC的5nm製程演講:
5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and High-Mobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications
根據網路上的消息:
TSMC to Discuss Their 5-nm CMOS Technology Platform at IEDM 2019
https://www.semiconductor-digest.com/2019/10/14/tsmc-to-discuss-their-5-nm-cmos-technology-platform-at-iedm-2019/
At the upcoming International Electron Devices Meeting (IEDM) in San Francisco December 7-11, Geoffrey Yeap will present the talk “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and High-Mobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications”.
Details of the 5-nm (N5) process have been slowly released over the last while, most recently at the Technology Symposium in April and the Open Innovation Platform Innovation Forum (OIP) last month, both in Santa Clara. Condensing the reported information from the two, and in no particular order, we have:
• Aimed at both high-performance computing and mobile customers
• Risk production started in March 2019; high volume ramp in 2Q’20 at the recently completed Gigafab 18 in Tainan (phase 1 equipment installation completed in March’19)
• There will be a N5P (performance) version a year later, with a +7% performance boost at constant power, or ~15% power reduction at constant perf over N5
• Logic density is increased by 1.8X, SRAM scaling is 0.75, and analog scaling is ~0.85 vs 7-nm
• Iso-power speed gain is 15%, or 30% lower power at the same speed compared with 7-nm.
• EUV use was emphasised
• There will be a high-mobility channel (Ge?) transistor
• Low-resistance contacts and vias.
• Transistor variants include an I/O transistor that can be either 1.5V or 1.2V, and an extreme LVT device 25% faster than the 7-nm equivalent.
• Via pillars and optimized metal in the HPC standard cells increase performance by 10%
• A 112Gbps SerDes is available.
• A super-high-density MIM-capacitor structure with 2X ff/µm2 and 2X insertion density, giving a 4% speed boost
• New low-K dielectric materials
• Metal Reactive Ion Etching (RIE), replacing Cu damascene for metal pitch < 30nm
• A graphene “cap” to reduce Cu interconnect resistivity
My thanks to Tom Dillinger at SemiWiki and Paul McLellan of Breakfast Bytes for their diligent reportage.
In the conference abstract details published by IEDM in their press kit, much of the above is reiterated. The logic density is a more detailed 1.84X, and the same 15% speed increase or 30% power drop over their 7-nm process are specified, as is EUV lithography (Fig. 2) and the high channel-mobility FinFET (Fig. 3). In addition, there are up to 7 Vts available (Fig.1). The company also says the high-density SRAM cell is the smallest ever reported, at 0.021µm2.
In a test circuit, a PAM4 SerDes transmitter demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The technology passed qualification with high yield and mass production is expected in 1H 2020. Fig. 1 below shows the 15% speed and density gains (left), and the seven Vt options.
Figure 1
Fig. 2 illustrates the comparison of five immersion masks with a single EUV mask, in what looks like a standard cell routing layer, i.e. M1 or M2. With a tentative Mx pitch of 30 nm, that would need SAQP or LE3, plus a couple of cut masks, replaced with one EUV litho step. Using MxP of 30 nm to calibrate, this image gives us a track height of ~175 nm (~5.8 track cell), a linear scaling of ~0.73 compared with the 7-nm process. And we can see that the pattern is quite a bit sharper.
Figure 2
Fig. 3 Improved drive current in stressed high-mobility devices (left); higher stress in fin determined by e-beam diffraction (right)
Fig. 3 (above) illustrates the improved drive current (+18%) in the high-mobility-channel transistor. There has been some comment that this might be a germanium channel (fin), but given the mis-match of the crystal lattices between Ge and Si, and the dislocations that would generate, it seems more likely that we have a PMOS SiGe channel similar to that used in the planar gate-first HKMG parts from the IBM consortium, containing up to 40% Ge.
The high-magnification TEM lattice images from a fin shown above indicate that the channel is the conventional <110> direction, though strangely the diffraction image on the right seems to be taken in the <100> direction.
Fig. 4 below is simply a plot of published SRAM cell sizes, showing the 0.021µm2 SRAM is the smallest reported to date.
Figure 4
Figure 5
In Fig. 5 above we have eye diagrams for PAM4 SerDes transmitters built on a 5-nm test chip demonstrating the 112 Gb/s mentioned earlier and the 130 Gb/s detailed in the abstract.
No mention is made in the IEDM preview of some of the earlier comments on the process; new low-k dielectrics is not surprising, but the dry etching of copper metallization is – if that is implemented, to my knowledge it will be a first. Could it be an application of the evolving technique of atomic-layer etching? And we have seen graphene metal caps in the literature, but again its use will be a first.
This looks to be an exciting presentation, but you will need patience and stamina to take it in – it is paper #36.7, scheduled at 4.05 pm on Wednesday 11th, the last paper of that session and almost the last paper of the conference!
