,未來幾年2330能再創股價高峰嗎?
td0036 wrote:
,未來幾年2330...(恕刪)
了解一下對手的動態！三星的腳步似乎有加快的跡象！
https://finance.technews.tw/2017/06/05/sumsang-ibm-intel/
狠甩英特爾，三星聯合 IBM 開發出首款 5 奈米製程晶片
被玩家戲稱為 「擠牙膏」 的半導體龍頭英特爾 (Intel) 製程進展，在英特爾已經確認會在 2017 年推出第八代酷睿處理器，而且新一代處理器依然採用 14 奈米製程生產的情況之下，根據國外科技網站 CNET 的報導，南韓科技大廠三星當前已經聯合了藍色巨人 IBM，研發出全球首款 5 奈米製程的晶片。相較英特爾還在堅守 14 奈米製程，在三星與 IBM 研發 出 5 奈米製程的晶片後，中間相隔著 10 奈米和 7 奈米世代製程，可說半導體晶片龍頭這下已經被狂甩了 3 個世代。
根據報導指出，日前三星聯合 IBM 宣佈了一項名為 nanosheets 的技術。受惠於該技術的突破，晶片製造商能夠將更多的電晶體容納到更小的晶片組裏。相較於目前製程所生產的晶片，三星預計在同樣水準的功耗底下，足足可以提升 40% 性能表現。或者，在獲得同樣的性能表現下，使用新技術的晶片僅需目前晶片的 1/4 功耗。
事實上，在過去數十年間，晶片製造產業的發展藉由技術的進步，使人類的生活帶來了史無前例的進步。這其中包括了第一台個人電腦的問世，第一臺智慧型手機的發明。而英特爾作為產業領頭羊，近些年的擠牙膏動作使其在晶片生產技術上落後於其他競爭對手。
如今，在三星、台積電都已經在晶片生產上快入 10 奈米世代的時候，英特爾還在堅持著 14 奈米製程。儘管，英特爾宣稱他的 14 奈米製程要比競爭對手的 10 奈米製程還要優秀。但不可否認的是，在製程技術上，英特爾確實已經開始落後。如今，在製成技術的進步步伐上，三星更是跨過了下一代 7 奈米製程世代，攜手 IBM 推出了全球首款 5 奈米製程的晶片。
由於更先進製造技術，就意味著能在更小的晶片上整合更多的電晶體，使晶片發揮更高的效能。IBM 的高層表示，由於 nonasheets 技術的 5 奈米晶片開發成功，未來將在更小的體積上提供更優的能耗表現。因此，在其他競爭對手紛紛有了新一步的製程計畫下，英特爾在半導體上的龍頭位置是否還能保持，就趨勢發展來看恐怕沒事太樂觀。
(首圖來源:shutterstock )
Nanosheet在英文裡有圖片說明！
https://semiengineering.com/samsung-unveils-scaling-packaging-roadmaps/
Samsung Unveils Scaling, Packaging Roadmaps
Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.
May 24th, 2017 - By: Ed Sperling
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Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise.
The moves put Samsung Foundry in direct competition with Intel, GlobalFoundries and TSMC, as well as Outsourced Semiconductor Assembly and Test vendors, across a wide swath of markets ranging from mobile devices to IoT, MRAM and RF. Samsung also announced its plan to begin risk production for 8nm LPP this year, and to begin using EUV in its 7nm LPP process next year. EUV is expected to reduce the number of photomasks required at that node by about 20.
Exactly what these numbers mean, and how they compare to other foundries, isn’t entirely clear, and there is discussion throughout semiconductor manufacturing sector that one foundry’s numbers don’t match another’s. But what is clear is that Samsung is attempting to pick up business at every node and half-node, including 8nm, 7nm, 6nm, 5nm, and 4nm, and it plans to introduce an 18nm version of its FD-SOI technology in 2019.
“This is now an independent foundry,” said Kelvin Low, senior director of foundry marketing at Samsung Foundry. “We will still leverage Samsung R&D and memory and logic. And we will utilize the company’s advanced packaging and manufacturing capacity. But we are now an independent business organization.”
This result, in effect, is being able to utilize the deep-pocket R&D of an IDM with a thriving end-market business in everything from televisions to smart phones, while also being able to utilize capacity of a newly constructed 300mm fab equipped with the latest technology, including EUV systems. Low said that with EUV the company is turning out 1,200 wafers per day, and he expects that number to improve.
Samsung has been in production on 10nm since late last year. The company issued a press release in March to that effect, saying it has shipped more than 70,000 wafers of its first-generation Low Power Early (LPE), although it didn’t discuss any additional details.
Joanne Itow, director of manufacturing at Semico Research, noted that all of the major foundries are scrambling to find out which process technologies will work best for which applications. Because many of the hot growth markets—automotive, industrial and regular IoT, augmented/virtual reality and medical—require new technology, it’s uncertain which process will win.
“Everyone is trying to figure out which process is best for which product, so foundries are opening up all of these processes,” Itow said. “This is coming from a variety of inquiries. Not every one can be a winner. Eventually, this will filter down to a few technologies. But customers do want different options this year, and we’re seeing the same thing happening with TSMC. They need to roll out something new. This is becoming a pervasive electronics applications market, and there are so many different types of products that we are seeing different processes to accommodate them.”
For Samsung in particular, this is a signal that the company is now courting a broader base of customers, she said. “In the past Samsung was very selective because they wanted to make sure they were successful with their product launches. Now, the next step is to get a broader base and to expand its foundry revenues.”
Samsung’s announcement also included developments at 8nm and 6nm. Samsung did not elaborate. But Sam Wang, a research vice president at Gartner, said the 8nm is a competitive move. “From a time-to-market point of view, it is inevitable that Samsung must offer a relaxed 7nm technology, in response to TSMC’s aggressive 7nm DUV schedule before EUV becomes ready,” he said. “Customers could not fully rely on Samsung’s 7nm EUV-only schedule, which has uncertainty because of the the exact progress of ASML (on EUV). In a way, Samsung’s 8LPP node is a relaxed 7nm node, which should be equivalent to TSMC’s N7, and Samsung’s 7LPP should be equivalent to TSMC’s N7+.”
Samsung also announced plans to introduce its first gate-all-around FET at 4nm in 2020 using EUV. This is the first time a foundry has publicly discussed a timetable for delivering GAA FETs, but roadmaps exist within a number of companies for several more nodes. That includes EUV lithography, GAA FETs using vertical and horizontal nanowires, and nanosheet FETs.
Kinam Kim, president of Samsung’s Semiconductor Business, said during a presentation at a recent event sponsored by Imec, a Belgium R&D organization, that the company sees a path to logic transistor scaling down to 1.5nm.
Then, using a 2D material called molybdenum disulfide (MoS2), Samsung believes it could scale logic technology even further. Samsung and others are exploring so-called MoS2 FETs. “We believe around 1nm is possible,” Kim said. Still in the R&D stage, MoS2 is a family of transition metal dichalcogenide (TMD) materials. The TMDs have remarkable electronic, optical and mechanical properties.
Fig. 1: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM.
In addition, Samsung announced its second-generation FD-SOI at 18nm in 2019 using immersion lithography. The company has been adding RF and other IP capabilities to its 28nm FD-SOI technology. Going forward, it plans to add embedded MRAM to FD-SOI, and eventually into finFET processes, as well. The company also is looking at FD-SOI for the automotive industry because it has a superior soft-error rate over bulk CMOS, said Low.
How this fares in the market is not clear. “On FD-SOI, we now have Samsung 28, 18nm, and GlobalFoundries’ 28, 22, and 12nm,” said Gartner’s Wang. “Since Samsung’s 18nm is independently developed by itself, it remains to be seen how GlobalFoundries will response to this 18nm offering.”
Back in CMOS, it appears that 10nm will be a long-lived node for Samsung. “We expect 10nm will be a very usable, long-life node,” Low said. “But some customers require a new node every year. So 7nm will be finFET on CMOS. 6nm will be smart scaling for area and power. 5nm will be finFET on CMOS. After that, we will show a post-finFET device, using a gate-all-around multi-bridge channel finFET.”
Perhaps the biggest surprise is a shift in the company’s advanced packaging. Samsung had hinted last year that it was looking for an alternative to silicon interposers because they are too expensive. The company is relying on a redistribution-layer (RDL) interposer to bridge logic to high-bandwidth memory, sidestepping commercial interposer technology for its 2.5D technology, and adding the same technology into its fan-outs.
Fig. 2: RDL interposer. Source: Samsung
Intel has introduced its own low-cost Embedded Multi-die Interconnect Bridge (EMIB), which is a silicon bridge that runs through the package substrate.
—Mark LaPedus contributed to this report.
原來除了gate first,gate last,還有最新的gate all around
http://www.eettaiwan.com/news/article/20160913NT01-Chip-Process-War-Heats-Up
半導體製程技術競爭升溫
IBS指出，在14奈米節點，FD-SOI的晶圓成本比FinFET低16.8%
（來源：IBS）
td0036 wrote:
＜2330＞ I8...(恕刪)
台積電7奈米製程傳痛宰三星，吃高通驍龍訂單
https://technews.tw/2017/06/12/qualcomm-ends-consignment-production-partnership-with-samsung-electronics-and-entrusts-production-of-7-nano-ap-with-tsmc/
台積電痛宰三星電子，搶下高通（Qualcomm）驍龍（Snapdragon）處理器大單？據傳台積電微縮製程進度大幅超前三星，高通變心，決定把 7 奈米晶片訂單轉給台積電。
南韓媒體 etnews 報導，三星替高通代工驍龍 820、830 系列晶片。不過業界消息透露，未來高通將轉單台積電，生產 7 奈米的次世代驍龍處理器。據了解，台積電今年 9 月將試產 7 奈米驍龍晶片，預定今年底到明年初間量產。據稱三星掉單原因是，去年下半台積電就提供客戶 7 奈米的製程設計套件（Process Design Kit，PDK），三星電子遠遠落後，要到今年 7 月才能發布 7 奈米 PDK 的 beta 測試版本。
報導稱，台積電眼光精準，跳過 10 奈米，直攻 7 奈米製程。三星電子則停留 10 奈米，近來才推出比 10 奈米略為升級的 8 奈米製程。從三星自家 Exynos 處理器生產進度也可發現，三星 7 奈米腳步遲緩。明年初量產的次世代 Exynos 晶片，將採 8 奈米，7 奈米 Exynos 晶片要到明年下半才會量產。
台積電不只製程研發腳步快，另一優勢是掌握先進封裝技術──「扇出型晶圓級封裝」（Fan-Out Wafer Level Package，FoWLP）。三星在這方面也落後台積，儘管全力研發比 FoWLP 更進步的「扇出型面板級封裝」（Fan-out Panel Level Package，FoPLP），但估計仍需一兩年時間才能採用。
之前外媒也有謠傳，高通次世代驍龍 845 晶片訂單，或許不再由三星吃下。
AndroidHeadlines 5 月報導，據了解高通次世代晶片驍龍 845 進入研發，預定 2018 年初問世，首發機種是三星電子的 Galaxy S9；一如今年上市的驍龍 835，首發機種為 Galaxy S8。目前驍龍 835 訂單由三星電子一家通吃。
消息稱，驍龍 835 採用 10 奈米製程，明年的驍龍 845 將晉級至 7 奈米製程，和前代相比，效能將提升 25%~35%。三星電子和台積都努力爭取訂單，目前台積電 7 奈米製程已進入試產。
據稱，除了高通之外，聯發科、中廠華為、Nvidia 也都有意改用 7 奈米製程。
（本文由 MoneyDJ新聞 授權轉載；首圖來源：高通）
延伸閱讀：
台積電受惠？傳三星封測技術落後，7、8 奈米擬外包
推動先進製程向下研發，台積電 2017 年研發經費將超過 22 億美元
三星推出 Exynos 9610 處理器，劍指高通驍龍 660 中階市場
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